New applications
such as multimedia or teleconferencing require high transmission power
of both, networks as well as terminal devices. Parallel transmission systems
offer significantly higher transmissions rates as compared to TCP/IP.
Due to parallel transmission functions, statecharts are predestinated
for their specification, from which a hardware-software implementation
is deduced semi-automatically.

Figure 2: Claude
Ackad and a prototype with an FPGA board
The parallel transmission
system Patroclos was modeled using statecharts. The mode of operation
of Patroclos, e.g. the connection establishment, can be visualized using
interactive simulations. The statechart model was divided into a hardware
partition for the time-critical parts and a software partition for the
uncritical parts. The latter ones were transformed into a machine program.
The hardware partition was transformed into a hardware description language
(HDL), which was further compiled with the Design Compiler of SYNOPSYS
and XACT of XILINX into a configuration of suitable field-programable
gate-arrays (FPGAs).
At the beginning,
the transmission functions were far too complex for the FPGAs employed.
The challenge was the appropriate modification of the statechart model
for the hardware partition to enable the generation of a configuration
of the XC4020 FPGAs using the tool chain STATEMATE-SYNOPSYS-XACT. Some
of the transmission functions required up to 100 attempts. Some resource
demanding statechart constructs were identified, which should be avoided.
These results have impact on future applications.
Ideas in high-speed
communication have to be tested practically. Therefore, a hardware-software
platform for Patroclos (Fig. 2) was developed in cooperation with the
research group High-Speed Communication and Multimedia Systems (Prof.
Zitterbart). It contains FPGAs, an i960 microprocessor for the machine
program of the software partition, and an ATM card.
The implementation
was successfully put into operation. Two hosts, each carrying one network
card, exchanged data. The interaction between i960 and FPGAs was logged
with a logic analyzer and special debug interfaces.
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