EXTERNAL PORTS

These are the external ports defined in the MHS file.

Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)

# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB sys_rst_pin I 1 sys_rst_s 1GLB vcc_pin O 1 net_vcc 2A fpga_0_LCD_OPTIONAL_GPIO_IO_pin IO 0:11 fpga_0_LCD_OPTIONAL_GPIO_IO 3B fpga_0_LEDs_8Bit_GPIO_IO_pin IO 0:7 fpga_0_LEDs_8Bit_GPIO_IO 4C fpga_0_ORGate_1_Res_1_pin O 1 fpga_0_ORGate_1_Res 5C fpga_0_ORGate_1_Res_2_pin O 1 fpga_0_ORGate_1_Res 6C fpga_0_ORGate_1_Res_pin O 1 fpga_0_ORGate_1_Res 7D sys_clk_pin I 1 dcm_clk_s  CLK  8D gnd_pin O 1 net_gnd 9E player_1_pin I 1 PLAYER1_IN 10E player_2_pin I 1 PLAYER2_IN 11E io_gpio_all_pin O 0:19 COUNT